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» Power efficient encoding techniques for off-chip data buses
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PATMOS
2004
Springer
13 years 10 months ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
13 years 10 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
13 years 9 months ago
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
William Fornaciari, Donatella Sciuto, Cristina Sil...
HIPC
2003
Springer
13 years 10 months ago
FV-MSB: A Scheme for Reducing Transition Activity on Data Buses
Power consumption becomes an important issue for modern processors. The off-chip buses consume considerable amount of total power [9,7]. One effective way to reduce power is to red...
Dinesh C. Suresh, Jun Yang 0002, Chuanjun Zhang, B...
DAC
2003
ACM
14 years 5 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...