9 search results - page 1 / 2 » Power reduction through iterative gate sizing and voltage sc... |
ISCAS
1999
IEEE
13 years 8 months ago
1999
IEEE
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
ISLPED
2003
ACM
13 years 9 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...