35 search results - page 1 / 7 » Power supply design parameters prediction for high performan... |
SLIP
2000
ACM
13 years 9 months ago
2000
ACM
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...
VLSID
1996
IEEE
13 years 8 months ago
1996
IEEE
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Inductive cross-talk within IC packaging is becoming a significant bottleneck in high-speed inter-chip communication. The parasitic inductance within IC packaging causes bounce o...