9 search results - page 1 / 2 » Power-Performance Implications of Thread-level Parallelism o... |
ISPASS
2005
IEEE
13 years 10 months ago
2005
IEEE
HPCA
1998
IEEE
13 years 9 months ago
1998
IEEE
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must explo...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...