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GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
9 years 4 months ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
9 years 4 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
FPL
1995
Springer
106views Hardware» more  FPL 1995»
9 years 2 months ago
Some Notes on Power Management on FPGA-Based Systems
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...
Eduardo I. Boemo, Guillermo González de Riv...
ICCD
2008
IEEE
160views Hardware» more  ICCD 2008»
9 years 5 months ago
An improved micro-architecture for function approximation using piecewise quadratic interpolation
We present a new micro-architecture for evaluating functions based on piecewise quadratic interpolation. The micro-architecture consists mainly of a look-up table and two multiply...
Shai Erez, Guy Even
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