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MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
13 years 11 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
SIGMETRICS
1998
ACM
13 years 10 months ago
Scheduling Policies to Support Distributed 3D Multimedia Applications
We consider the problem of scheduling tasks with unpredictable service times on distinct processing nodes so as to meet a real-time deadline, given that all communication among no...
Thu D. Nguyen, John Zahorjan
LCPC
2000
Springer
13 years 9 months ago
Automatic Coarse Grain Task Parallel Processing on SMP Using OpenMP
This paper proposes a simple and efficient implementation method for a hierarchical coarse grain task parallel processing scheme on a SMP machine. OSCAR multigrain parallelizing c...
Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka
IPPS
2010
IEEE
13 years 3 months ago
Speculative execution on multi-GPU systems
Abstract--The lag of parallel programming models and languages behind the advance of heterogeneous many-core processors has left a gap between the computational capability of moder...
Gregory F. Diamos, Sudhakar Yalamanchili