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CASES
2009
ACM
13 years 12 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing speciļ¬cations e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
CODES
2005
IEEE
13 years 11 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
SIGKDD
2010
259views more  SIGKDD 2010»
13 years 1 days ago
Activity recognition using cell phone accelerometers
Mobile devices are becoming increasingly sophisticated and the latest generation of smart cell phones now incorporates many diverse and powerful sensors. These sensors include GPS...
Jennifer R. Kwapisz, Gary M. Weiss, Samuel Moore
IPPS
2008
IEEE
13 years 11 months ago
A plug-and-play model for evaluating wavefront computations on parallel architectures
This paper develops a plug-and-play reusable LogGP model that can be used to predict the runtime and scaling behavior of different MPI-based pipelined wavefront applications runni...
Gihan R. Mudalige, Mary K. Vernon, Stephen A. Jarv...
MOBICOM
2004
ACM
13 years 10 months ago
A scalable model for channel access protocols in multihop ad hoc networks
A new modeling framework is introduced for the analytical study of medium access control (MAC) protocols operating in multihop ad hoc networks. The model takes into account the eļ...
Marcelo M. Carvalho, Jose Joaquin Garcia-Luna-Acev...