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ASAP
2002
IEEE
85views Hardware» more  ASAP 2002»
13 years 9 months ago
Predictable Instruction Caching for Media Processors
The determinism of instruction cache performance can be considered a major problem in multi-media devices which hope to maximise their quality of service. If instructions are evic...
James Irwin, David May, Henk L. Muller, Dan Page
OTM
2004
Springer
13 years 10 months ago
A Time Predictable Instruction Cache for a Java Processor
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
Martin Schoeberl
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
13 years 11 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
14 years 1 months ago
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
ICCAD
2001
IEEE
272views Hardware» more  ICCAD 2001»
14 years 1 months ago
NetBench: A Benchmarking Suite for Network Processors
— In this study we introduce NetBench, a benchmarking suite for network processors. NetBench contains a total of 9 applications that are representative of commercial applications...
Gokhan Memik, William H. Mangione-Smith, Wendong H...