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» Predictable performance in SMT processors
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HPCA
2008
IEEE
14 years 5 months ago
PaCo: Probability-based path confidence prediction
A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applica...
Kshitiz Malik, Mayank Agarwal, Vikram Dhar, Matthe...
DSD
2004
IEEE
126views Hardware» more  DSD 2004»
13 years 8 months ago
Implicit vs. Explicit Resource Allocation in SMT Processors
In a Simultaneous Multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among ...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
SIGOPS
2008
122views more  SIGOPS 2008»
13 years 4 months ago
Do commodity SMT processors need more OS research?
The availability of Simultaneous Multithreading (SMT) in commodity processors such as the Pentium 4 (P4) has raised interest among OS researchers. While earlier simulation studies...
Yaoping Ruan, Vivek S. Pai, Erich M. Nahum, John M...
IPPS
2010
IEEE
13 years 2 months ago
A low cost split-issue technique to improve performance of SMT clustered VLIW processors
Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreadi...
Manoj Gupta, Fermín Sánchez, Josep L...
ISHPC
2003
Springer
13 years 10 months ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos