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HPCA
1997
IEEE
13 years 10 months ago
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication. In compiler-synthesized dynamic branch prediction, the compiler g...
David I. August, Daniel A. Connors, John C. Gyllen...
ISCA
1997
IEEE
98views Hardware» more  ISCA 1997»
13 years 9 months ago
Target Prediction for Indirect Jumps
As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be th...
Po-Yung Chang, Eric Hao, Yale N. Patt
ICCD
2002
IEEE
130views Hardware» more  ICCD 2002»
14 years 3 months ago
Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors
This paper presents a detailed branch characterization of an Oracle based commercial on-line transaction processing workload, Oracle Database Benchmark (ODB), running on an IA32 p...
Murali Annavaram, Trung A. Diep, John Paul Shen
MICRO
1998
IEEE
144views Hardware» more  MICRO 1998»
13 years 10 months ago
Analyzing the Working Set Characteristics of Branch Execution
To achieve highly accurate branch prediction, it is necessary not only to allocate more resources to branch prediction hardware but also to improve the understanding of branch exe...
Sangwook P. Kim, Gary S. Tyson
ICS
1998
Tsinghua U.
13 years 10 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...