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3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
13 years 10 months ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...
FLAIRS
2007
13 years 7 months ago
Memory-Prediction Framework for Pattern Recognition: Performance and Suitability of the Bayesian Model of Visual Cortex
This paper explores an inferential system for recognizing visual patterns. The system is inspired by a recent memoryprediction theory and models the high-level architecture of the...
Saulius Juozas Garalevicius
EUROPAR
1997
Springer
13 years 9 months ago
Prefetching and Multithreading Performance in Bus-Based Multiprocessors with Petri Nets
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
Edward D. Moreno, Sergio Takeo Kofuji, Marcelo H. ...
SPAA
1995
ACM
13 years 9 months ago
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent yea...
Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias,...
WOSP
2010
ACM
14 years 12 days ago
Analytical modeling of lock-based concurrency control with arbitrary transaction data access patterns
Nowadays the 2-Phase-Locking (2PL) concurrency control algorithm still plays a core rule in the construction of transactional systems (e.g. database systems and transactional memo...
Pierangelo di Sanzo, Roberto Palmieri, Bruno Cicia...