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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 2 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
BROADNETS
2007
IEEE
13 years 11 months ago
Fair bandwidth allocation framework for heterogeneous multi-radio Wireless Mesh Networks
Abstract—To reap the benefits of advances in wireless technologies as well as provide backward compatibility with current investments, future wireless routers that constitute th...
Shree Raman, Aura Ganz, Ramgopal R. Mettu
CP
2003
Springer
13 years 10 months ago
Incremental Computation of Resource-Envelopes in Producer-Consumer Models
Abstract. Interleaved planning and scheduling employs the idea of extending partial plans by regularly heeding to the scheduling constraints during search. One of the techniques us...
T. K. Satish Kumar
TIP
2008
133views more  TIP 2008»
13 years 5 months ago
A Recursive Model-Reduction Method for Approximate Inference in Gaussian Markov Random Fields
This paper presents recursive cavity modeling--a principled, tractable approach to approximate, near-optimal inference for large Gauss-Markov random fields. The main idea is to su...
Jason K. Johnson, Alan S. Willsky
CVPR
2012
IEEE
11 years 7 months ago
A learning-based framework for depth ordering
Depth ordering is instrumental for understanding the 3D geometry of an image. We as humans are surprisingly good ordering even with abstract 2D line drawings. In this paper we pro...
Zhaoyin Jia, Andrew C. Gallagher, Yao-Jen Chang, T...