18 search results - page 1 / 4 » Probabilistic maximum error modeling for unreliable logic ci... |
GLVLSI
2007
IEEE
13 years 8 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
- A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and ...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
Switching model captures the data-driven uncertainty in logic circuits in a comprehensive probabilistic framework. Switching is a critical factor that influences dynamic, active ...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
TCAD
1998
13 years 4 months ago
1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...