51 search results - page 1 / 11 » Process Variation Tolerant 3T1D-Based Cache Architectures |
MICRO
2007
IEEE
13 years 10 months ago
2007
IEEE
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
CASES
2009
ACM
13 years 7 months ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
PRDC
2006
IEEE
13 years 10 months ago
2006
IEEE
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...