4 search results - page 1 / 1 » Process variation characterization of chip-level multiproces... |
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
—Associated with the ever growing integration scales is the increase in process variability. In the context of networkon-chip, this variability affects the maximum frequency that...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
ISQED
2010
IEEE
13 years 11 months ago
2010
IEEE
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...