142 search results - page 1 / 29 » Processor Memory Co-Exploration on Multiple Abstraction Leve... |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
EMSOFT
2001
Springer
13 years 10 months ago
2001
Springer
ltiple Levels of Abstractions in Embedded Software Design Jerry R. Burch1, Roberto Passerone1, and Alberto L. Sangiovanni-Vincentelli2 1 Cadence Berkeley Laboratories, Berkeley CA ...
HPCA
2007
IEEE
14 years 6 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
ISCAPDCS
2004
13 years 7 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
JSSPP
2000
Springer
13 years 9 months ago
2000
Springer
Abstract. Buffered coscheduling is a new methodology that can substantially increase resource utilization, improve response time, and simplify the development of the run-time suppo...