4 search results - page 1 / 1 » Profile-guided microarchitectural floorplanning for deep sub... |
DAC
2004
ACM
14 years 5 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout....
MICRO
1999
IEEE
13 years 8 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— In this paper, we propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. ...