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» Protocol verification using flows: An industrial experience
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ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 2 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
CODES
2005
IEEE
13 years 10 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
AIME
2003
Springer
13 years 8 months ago
Experiences in the Formalisation and Verification of Medical Protocols
Abstract. Medical practice protocols or guidelines are statements to assist practitioners and patient decisions about appropriate health care for specific circumstances. In order t...
Mar Marcos, Michael Balser, Annette ten Teije, Fra...
AINA
2003
IEEE
13 years 8 months ago
Formal Verification of Condition Data Flow Diagrams for Assurance of Correct Network Protocols
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
Shaoying Liu
ICSE
2009
IEEE-ACM
13 years 2 months ago
Model checking flight control systems: The Airbus experience
This paper presents experiments realized by Airbus on model checking a safety critical system, lessons learnt and ways forward to extend the industrial use of formal verification ...
Thomas Bochot, Pierre Virelizier, Hél&egrav...