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ICCAD
2000
IEEE
102views Hardware» more  ICCAD 2000»
13 years 9 months ago
Provably Good Global Buffering Using an Available Buffer Block Plan
To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and b...
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu,...
ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
14 years 1 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
14 years 5 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
AI
2010
Springer
13 years 4 months ago
Kernel functions for case-based planning
Case-based planning can take advantage of former problem-solving experiences by storing in a plan library previously generated plans that can be reused to solve similar planning p...
Ivan Serina
ICDCS
2008
IEEE
13 years 11 months ago
MC2: Multiple Clients on a Multilevel Cache
In today’s networked storage environment, it is common to have a hierarchy of caches where the lower levels of the hierarchy are accessed by multiple clients. This sharing can h...
Gala Yadgar, Michael Factor, Kai Li, Assaf Schuste...