37 search results - page 8 / 8 » Pseudo-Circuit: Accelerating Communication for On-Chip Inter... |
IEEEHPCS
2010
13 years 3 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
PVG
2003
IEEE
13 years 10 months ago
2003
IEEE
Parallel volume rendering offers a feasible solution to the large data visualization problem by distributing both the data and rendering calculations among multiple computers con...