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MICRO
1998
IEEE
128views Hardware» more  MICRO 1998»
13 years 8 months ago
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
13 years 4 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
MICRO
2005
IEEE
125views Hardware» more  MICRO 2005»
13 years 10 months ago
Improving Region Selection in Dynamic Optimization Systems
The performance of a dynamic optimization system depends heavily on the code it selects to optimize. Many current systems follow the design of HP Dynamo and select a single interp...
David Hiniker, Kim M. Hazelwood, Michael D. Smith
VEE
2006
ACM
178views Virtualization» more  VEE 2006»
13 years 10 months ago
Impact of virtual execution environments on processor energy consumption and hardware adaptation
During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual executio...
Shiwen Hu, Lizy Kurian John