3 search results - page 1 / 1 » Q-Tree: A New Iterative Improvement Approach for Buffered In... |
ISVLSI
2003
IEEE
13 years 9 months ago
2003
IEEE
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
VLSID
1999
IEEE
13 years 8 months ago
1999
IEEE
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
ISPD
2003
ACM
13 years 9 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...