2 search results - page 1 / 1 » Quantifying Thread Vulnerability for Multicore Architectures |
PDP
2011
IEEE
12 years 8 months ago
2011
IEEE
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
ISPASS
2007
IEEE
13 years 10 months ago
2007
IEEE
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...