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» Queue Machines: Hardware Compilation in Hardware
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ISCA
1999
IEEE
218views Hardware» more  ISCA 1999»
13 years 8 months ago
Maps: A Compiler-Managed Memory System for Raw Machines
Rajeev Barua, Walter Lee, Saman P. Amarasinghe, An...
MICRO
2000
IEEE
137views Hardware» more  MICRO 2000»
13 years 8 months ago
Relational profiling: enabling thread-level parallelism in virtual machines
Virtual machine service threads can perform many tasks in parallel with program execution such as garbage collection, dynamic compilation, and profile collection and analysis. Har...
Timothy H. Heil, James E. Smith
CASES
2006
ACM
13 years 9 months ago
Automatic performance model construction for the fast software exploration of new hardware designs
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
John Cavazos, Christophe Dubach, Felix V. Agakov, ...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
13 years 10 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
FPL
1995
Springer
152views Hardware» more  FPL 1995»
13 years 7 months ago
Compiling Ruby into FPGAs
This paper presents an overview of a prototype hardware compiler which compiles a design expressed in the Ruby language into FPGAs. The features of two important modules, the re ne...
Shaori Guo, Wayne Luk