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GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 8 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
13 years 8 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
CASES
2004
ACM
13 years 8 months ago
Scalable custom instructions identification for instruction-set extensible processors
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. However, it is computationally expensive to automaticall...
Pan Yu, Tulika Mitra
SAMOS
2010
Springer
13 years 2 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
ASPDAC
1999
ACM
98views Hardware» more  ASPDAC 1999»
13 years 8 months ago
Generation of Interpretive and Compiled Instruction Set Simulators
Abstract Due to the large variety of di erent embedded processor types, retargetable software development tools, such as compilers and simulators, have received attention recently....
Rainer Leupers, Johann Elste, Birger Landwehr