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» RTL Power Optimization with Gate-Level Accuracy
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ICCAD
2003
IEEE
120views Hardware» more  ICCAD 2003»
14 years 1 months ago
RTL Power Optimization with Gate-Level Accuracy
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
Qi Wang, Sumit Roy
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
13 years 8 months ago
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
Markus Bühler, Matthias Papesch, K. Kapp, Utz...
ISLPED
2007
ACM
109views Hardware» more  ISLPED 2007»
13 years 5 months ago
A multi-model power estimation engine for accuracy optimization
RTL power macromodeling is a mature research topic with a variety of equation and table-based approaches. Despite its maturity, macromodeling is not yet widely accepted as an indu...
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Rober...