6 search results - page 1 / 2 » RTL Scan Design for Skewed-Load At-speed Test under Power Co... |
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...