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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 5 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
RSP
1999
IEEE
122views Control Systems» more  RSP 1999»
13 years 9 months ago
Incremental Compilation for Logic Emulation
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...
Russell Tessier
CODES
2005
IEEE
13 years 10 months ago
Dynamic phase analysis for cycle-close trace generation
For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system em...
Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh...
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
13 years 10 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...
GLOBECOM
2009
IEEE
13 years 11 months ago
QOMB: A Wireless Network Emulation Testbed
—In this paper we present QOMB, a testbed we designed and implemented for the evaluation of wireless network systems, protocols and applications. The testbed uses the wireless ne...
Razvan Beuran, Lan Tien Nguyen, Toshiyuki Miyachi,...