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» Rate Optimal VLSI Design from Data Flow Graph
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IPPS
2005
IEEE
13 years 11 months ago
Fault-Tolerant Parallel Applications with Dynamic Parallel Schedules
Commodity computer clusters are often composed of hundreds of computing nodes. These generally off-the-shelf systems are not designed for high reliability. Node failures therefore...
Sebastian Gerlach, Roger D. Hersch
CODES
2007
IEEE
14 years 4 days ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
GECCO
2008
Springer
129views Optimization» more  GECCO 2008»
13 years 6 months ago
Fitness calculation approach for the switch-case construct in evolutionary testing
A well-designed fitness function is essential to the effectiveness and efficiency of evolutionary testing. Fitness function design has been researched extensively. For fitness ...
Yan Wang, Zhiwen Bai, Miao Zhang, Wen Du, Ying Qin...
SIGGRAPH
1994
ACM
13 years 10 months ago
IRIS performer: a high performance multiprocessing toolkit for real-time 3D graphics
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
John Rohlf, James Helman
MASCOTS
2004
13 years 7 months ago
An Optimisation Model for a Two-Node Router Network
Architectural designs for routers and networks of routers to support mobile communication are analysed for their end-to-end performance using a simple Markov model. In view of the...
Nalan Gülpinar, Peter G. Harrison, Berç...