9 search results - page 1 / 2 » Reconfigurable Shuffle Network Design in LDPC Decoders |
ASAP
2006
IEEE
13 years 6 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
SOCC
2008
IEEE
13 years 10 months ago
2008
IEEE
Abstract— In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapa...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
GLOBECOM
2009
IEEE
13 years 2 months ago
2009
IEEE
We consider the uplink of two mobile stations with the help of one common relay. Recently, joint network-channel coding based on LDPC codes was proposed for this setup where the ch...
DASIP
2010
12 years 11 months ago
2010
This paper proposes an automatic design flow from userfriendly design to efficient implementation of video processing systems. This design flow starts with the use of coarsegrain ...