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DATE
1999
IEEE
194views Hardware» more  DATE 1999»
13 years 9 months ago
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
Bharat P. Dav
CDES
2006
158views Hardware» more  CDES 2006»
13 years 6 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
13 years 9 months ago
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
Dirk Koch, Christian Haubelt, Jürgen Teich
FCCM
2009
IEEE
322views VLSI» more  FCCM 2009»
13 years 9 months ago
On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat)
Abstract--The Cibola Flight Experiment (CFE) is an experimental small satellite developed at the Los Alamos National Laboratory to demonstrate the feasibility of using FPGA-based r...
Michael P. Caffrey, Keith Morgan, Diane Roussel-Du...
FPGA
2001
ACM
139views FPGA» more  FPGA 2001»
13 years 9 months ago
A memory coherence technique for online transient error recovery of FPGA configurations
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
Wei-Je Huang, Edward J. McCluskey