13 search results - page 2 / 3 » Recovery Mechanisms for Dual Core Architectures |
DSN
2008
IEEE
13 years 11 months ago
2008
IEEE
In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by which co...
ISCAPDCS
2003
13 years 6 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
CLUSTER
2006
IEEE
13 years 11 months ago
2006
IEEE
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
CASCON
2004
13 years 6 months ago
2004
We report on initial experiments in tree locking schemes for compiled database applications. Such applications have a repository style of architecture in which a collection of sof...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...