466 search results - page 1 / 94 » Reduce, reuse |
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...
APCSAC
2003
IEEE
13 years 9 months ago
2003
IEEE
This paper proposes an approach for reducing access count to register-files based on operand data reuse. The key idea is to compare source and destination operands of the current ...
HIPEAC
2005
Springer
13 years 9 months ago
2005
Springer
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
SBCCI
2004
ACM
13 years 9 months ago
2004
ACM
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
CVPR
2008
IEEE
14 years 6 months ago
2008
IEEE
In this paper, we present novel techniques that improve the computational and memory efficiency of algorithms for solving multi-label energy functions arising from discrete MRFs o...