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ICS
2000
Tsinghua U.
13 years 9 months ago
2000
Tsinghua U.
As the performance gap between the CPU and main memory continues to grow, techniques to hide memory latency are essential to deliver a high performance computer system. Prefetchin...
IEEEPACT
1998
IEEE
13 years 9 months ago
1998
IEEE
Compile-time scheduling is one approach to extract parallelism which has proved effective when the execution behavior is predictable. Unfortunately, the performance of most priori...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
MICRO
2002
IEEE
13 years 10 months ago
2002
IEEE
Data prefetching effectively reduces the negative effects of long load latencies on the performance of modern processors. Hardware prefetchers employ hardware structures to predic...