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» Reducing State Changes with a Pipeline Buffer
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HPCA
2006
IEEE
14 years 5 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
VC
2010
182views more  VC 2010»
13 years 3 months ago
Color invariant chroma keying and color spill neutralization for dynamic scenes and cameras
Abstract In this article we show, how temporal backdrops that alternately change their color rapidly at recording rate can aid chroma keying by transforming color spill into a neut...
Anselm Grundhöfer, Daniel Kurz, Sebastian Thi...
CGF
2008
139views more  CGF 2008»
13 years 5 months ago
CHC++: Coherent Hierarchical Culling Revisited
We present a new algorithm for efficient occlusion culling using hardware occlusion queries. The algorithm significantly improves on previous techniques by making better use of te...
Oliver Mattausch, Jirí Bittner, Michael Wim...
MICRO
2005
IEEE
105views Hardware» more  MICRO 2005»
13 years 10 months ago
Incremental Commit Groups for Non-Atomic Trace Processing
We introduce techniques to support efficient non-atomic execution of very long traces on a new binary translation based, x86-64 compatible VLIW microprocessor. Incrementally comm...
Matt T. Yourst, Kanad Ghose
OSDI
2008
ACM
14 years 5 months ago
Greening the Switch
Active research is being conducted in reducing power consumption of all the components of the Internet. To that end, we propose schemes for power reduction in network switches - T...
Ganesh Ananthanarayanan, Randy H. Katz