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» Reducing register ports for higher speed and lower energy
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ICCD
2006
IEEE
275views Hardware» more  ICCD 2006»
14 years 1 months ago
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
Tinoosh Mohsenin, Bevan M. Baas
CORR
2010
Springer
177views Education» more  CORR 2010»
13 years 2 months ago
Dynamic Scheduling of Skippable Periodic Tasks with Energy Efficiency in Weakly Hard Real-Time System
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
Santhi Baskaran, P. Thambidurai
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
13 years 10 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
JCM
2010
126views more  JCM 2010»
13 years 3 months ago
Adding Redundancy to Replication in Window-aware Delay-tolerant Routing
— This paper presents a resource-efficient protocol for opportunistic routing in delay-tolerant networks (DTN). First, our approach exploits the context of mobile nodes (speed, ...
Gabriel Sandulescu, Simin Nadjm-Tehrani