43 search results - page 1 / 9 » Reducing the Energy of Speculative Instruction Schedulers |
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
Energy dissipation from the issue queue and register file constitutes a large portion of the overall energy budget of an aggressive dynamically scheduled microprocessor. We propo...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce ...
ISCA
1998
IEEE
13 years 8 months ago
1998
IEEE
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
HIPEAC
2007
Springer
13 years 10 months ago
2007
Springer
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...