43 search results - page 8 / 9 » Reducing the Energy of Speculative Instruction Schedulers |
CSREAESA
2004
13 years 6 months ago
2004
The growing software content in various battery-driven embedded systems has led to significant interest in technologies for energy-efficient embedded software. While lowenergy sof...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
ICCD
2008
IEEE
14 years 2 months ago
2008
IEEE
— Embedded processors are required to achieve high performance while running on batteries. Thus, they must exploit all the possible means available to reduce energy consumption w...