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» Redundancy in Instruction Sequences of Computer Programs
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HPCA
2008
IEEE
14 years 5 months ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang
IFL
2004
Springer
13 years 10 months ago
A Virtual Machine for Functional Logic Computations
Abstract. We describe the architecture of a virtual machine for executing functional logic programming languages. A distinguishing feature of our machine is that it preserves the o...
Sergio Antoy, Michael Hanus, Jimeng Liu, Andrew P....
EWNLG
1993
13 years 9 months ago
Generating Grammatical and Lexical Anaphora in Assembly Instructional Texts
In this paper, we discuss the problem of generating natural anaphora in assembly instructional texts. We rst present a detailed account of grammatical and lexical anaphora and we e...
Leila Kosseim, Agnès Tutin, Richard I. Kitt...
IEEEPACT
1998
IEEE
13 years 9 months ago
Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
Artur Klauser, Todd M. Austin, Dirk Grunwald, Brad...
EUROPAR
2001
Springer
13 years 9 months ago
Load Redundancy Elimination on Executable Code
Optimizations performed at link time or directly applied to nal program executables have received increased attention in recent years. This paper discuss the discovery and elimina...
Manel Fernández, Roger Espasa, Saumya K. De...