17 search results - page 4 / 4 » Redundant-via enhanced maze routing for yield improvement |
DAC
2006
ACM
14 years 6 months ago
2006
ACM
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...