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ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
14 years 1 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
ISPD
2000
ACM
124views Hardware» more  ISPD 2000»
13 years 9 months ago
A performance optimization method by gate sizing using statistical static timing analysis
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
Masanori Hashimoto, Hidetoshi Onodera
DAC
2005
ACM
14 years 5 months ago
Statistical static timing analysis: how simple can we get?
Chirayu S. Amin, Noel Menezes, Kip Killpack, Flore...
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
13 years 11 months ago
On hierarchical statistical static timing analysis
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
Bing Li, Ning Chen, Manuel Schmidt, Walter Schneid...
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
13 years 10 months ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...