17 search results - page 2 / 4 » Register Allocation and Binding for Low Power |
ICCAD
2006
IEEE
13 years 11 months ago
2006
IEEE
Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage wou...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
CODES
2001
IEEE
13 years 9 months ago
2001
IEEE
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
HPCA
2012
IEEE
12 years 28 days ago
2012
IEEE
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...