32 search results - page 1 / 7 » Register File Design Considerations in Dynamically Scheduled... |
HPCA
1996
IEEE
13 years 8 months ago
1996
IEEE
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
DAC
1996
ACM
13 years 8 months ago
1996
ACM
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
HPCA
2005
IEEE
14 years 4 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
CODES
2001
IEEE
13 years 8 months ago
2001
IEEE
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
MICRO
2000
IEEE
13 years 4 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...