3 search results - page 1 / 1 » Register Transfer Operation Analysis during Data Path Verifi... |
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
A control part ? data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a ...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...