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APCCAS
2002
IEEE
138views Hardware» more  APCCAS 2002»
13 years 10 months ago
A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter
This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as ...
A. Tamtrakarn, N. Wongkomet
DAC
2006
ACM
14 years 6 months ago
Optimality study of resource binding with multi-Vdds
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...
Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
ASYNC
2002
IEEE
124views Hardware» more  ASYNC 2002»
13 years 10 months ago
Synchronous Interlocked Pipelines
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Pe...