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ICCD
2006
IEEE
94views Hardware» more  ICCD 2006»
14 years 1 months ago
Reliability Support for On-Chip Memories Using Networks-on-Chip
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...
Federico Angiolini, David Atienza, Srinivasan Mura...
EDCC
2008
Springer
13 years 6 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
13 years 10 months ago
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip
In this paper is proposed a technique to integrate and simulate a dynamic memory in a multiprocessor framework based on C/C++/SystemC. Using host machine’s memory management cap...
Oreste Villa, Patrick Schaumont, Ingrid Verbauwhed...
IMS
2000
123views Hardware» more  IMS 2000»
13 years 8 months ago
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of...
David Judd, Katherine A. Yelick, Christoforos E. K...
MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
13 years 11 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos