6 search results - page 1 / 2 » Restrictive Compression Techniques to Increase Level 1 Cache... |
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
ARCS
2006
Springer
13 years 8 months ago
2006
Springer
Abstract. Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. ...
ICCD
2001
IEEE
14 years 1 months ago
2001
IEEE
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
HPCA
2005
IEEE
14 years 4 months ago
2005
IEEE
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hie...
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...