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DDECS
2008
IEEE
185views Hardware» more  DDECS 2008»
13 years 11 months ago
Fast Boolean Minimizer for Completely Specified Functions
: We propose a simple and fast two-level minimization algorithm for completely specified functions in this paper. The algorithm is based on processing ternary trees. A ternary tree...
Petr Fiser, Pemysl Rucký, Irena Vanov&aacut...
ICCAD
1999
IEEE
119views Hardware» more  ICCAD 1999»
13 years 9 months ago
Factoring logic functions using graph partitioning
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
Martin Charles Golumbic, Aviad Mintz
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
13 years 11 months ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...
DAC
2003
ACM
14 years 6 months ago
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Br...
SACRYPT
2005
Springer
138views Cryptology» more  SACRYPT 2005»
13 years 10 months ago
On the (Im)Possibility of Practical and Secure Nonlinear Filters and Combiners
A vast amount of literature on stream ciphers is directed to the cryptanalysis of LFSR-based filters and combiners, resulting in various attack models such as distinguishing attac...
An Braeken, Joseph Lano