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» Reuse-Driven Tiling for Improving Data Locality
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ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
13 years 10 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
BMCBI
2010
154views more  BMCBI 2010»
13 years 5 months ago
An algorithm for automated closure during assembly
Background: Finishing is the process of improving the quality and utility of draft genome sequences generated by shotgun sequencing and computational assembly. Finishing can invol...
Sergey Koren, Jason R. Miller, Brian Walenz, Grang...
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 4 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....