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ICDE
2006
IEEE
130views Database» more  ICDE 2006»
14 years 5 months ago
Revision Processing in a Stream Processing Engine: A High-Level Design
Esther Ryvkina, Anurag Maskey, Mitch Cherniack, St...
EDBT
2008
ACM
171views Database» more  EDBT 2008»
14 years 4 months ago
Replay-based approaches to revision processing in stream query engines
Data stream processing systems have become ubiquitous in academic and commercial sectors, with application areas that include financial services, network traffic analysis, battlef...
Anurag Maskey, Mitch Cherniack
IPPS
2007
IEEE
13 years 10 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
FDL
2007
IEEE
13 years 10 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
TCAD
2010
121views more  TCAD 2010»
12 years 11 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta